Project Background and Customer Pain Point
The customer was developing a domestic industrial constant-temperature bath controller targeting an extremely high control accuracy of ±0.1°C. The design required wide-temperature operation from -40°C to +85°C, 4-channel PT100 acquisition and 2-channel TEC (thermoelectric cooler) drive.
However, during early 4-layer prototype testing, the customer encountered a highly unusual phenomenon: after five minutes of full-load TEC operation, PT100 readings began drifting slowly at a rhythm of 1.2 Hz. The drift was not random jumping — it rose and fell as regularly as breathing.
Diagnostic premise: this was not a faulty ADC, nor a mistuned PID algorithm. The PCB was "talking" — reporting through temperature rise, coupling and impedance mismatch that electrical, thermal and field behavior are never three separate things, but three faces of one system.
Root Cause Investigation: From Symptom to Physical Failure Point
Facing this "breathing phenomenon," the AnyPCBA engineering team worked alongside the customer on a systematic, hardware-level investigation:
Thermal imaging: the area around the LDO (TPS7A47) showed a 15°C temperature rise, and the pad temperature of the core voltage reference REF3025 climbed to 68°C (ambient 25°C), far beyond its temperature-drift specification.
Spectrum capture: a strong peak at 1.23 MHz was captured at the input of the instrumentation amplifier INA128 — the second harmonic of the Buck switching frequency (1.2 MHz).
Coupled thermal-electrical simulation: ANSYS Icepak combined with HFSS confirmed a critical noise injection path: 1.23 MHz switching noise → LDO output → REF3025 input → ADC REF pin.
Conclusion: an LDO is not a filter — it is only the last door. If switching-noise "garbage" piles up in front of that door, even the best door cannot stop the smell from seeping through.
System Redesign: Three Critical Lines from AnyPCBA's Perspective
Solving this systemic offset required more than "adding a capacitor." It required a coordinated thermal-electrical-magnetic reconstruction at PCB scale.
Critical Line 1: How to Make the Power Path "Quiet"
The power delivery chain was rebuilt as a three-stage purification channel:
Entry purification (conducted side): a π-type LC filter (22 μF X7R + 1 μH ferrite bead + 10 μF ceramic). The ferrite bead had to meet 100 Ω @ 100 MHz with DCR < 0.15 Ω.
Mid-stage isolation (radiated side): the common-mode path was cut, with a 47 μF low-ESR tantalum capacitor and an LT3045 placed ahead of the LDO (its PSRR reaches 79 dB at 1 MHz).
End-point anchoring (chip side): 0.1 μF + 10 μF in parallel at the ADC VDD pin, with the 0.1 μF placed directly against the pin and a trace length ≤ 0.5 mm, forming a local "voltage rigid body."
The truly critical detail was hidden in the ground. Rather than the common "split ground + 0 Ω bridge," the AGND and DGND connection point was placed precisely on the GND pad of the LT3045 input capacitor — the point where analog-domain ground potential is most stable (it has absorbed the Buck ripple but has not yet been disturbed by LDO ripple), anchoring zero potential at the noise trough.
In firmware, a forced 10 ms power-on delay closed the "first-sample anomaly" loophole caused by unsynchronized LDO startup timing.
Critical Line 2: Where to Place Thermally Sensitive Components
Engineers often say "keep away from heat sources," but the real answer lies in the thermal conductivity of copper foil. PCB copper is an efficient heat conductor (λ ≈ 390 W/m·K), roughly 1300 times faster than FR-4. "Isolating heat sources" therefore means "cutting the copper thermal path."
AnyPCBA divided the board into three physical thermal zones:
Heat source zone (bottom right): a 2 mm wide thermal slot on the bottom layer cut vertical heat conduction; no vias to inner-layer ground were allowed beneath power device pads, preventing heat from pouring directly into inner layers.
Buffer zone (center): copper pour used a 50% duty-cycle grid pattern, preserving signal return paths while weakening thermal spreading.
Sensitive zone (top left): large-area copper pour was prohibited around temperature-drift-sensitive parts such as REF3025, leaving only the necessary ground traces — because for drift-sensitive devices, a ground plane is a thermal blanket, not a shield.
In addition, a 20 mm² independent copper pad was placed beneath REF3025 and connected to layer 3 through eight 0.3 mm vias. This "thermal anchor" design reduced junction temperature by 3.2°C, translating to a ±0.03°C improvement in PT100 measurement.
Critical Line 3: How to Build the Multilayer Stack-Up
The board was upgraded to 8 layers. A stack-up is not a pile of layers — it is a plan for the paths of fields.
A "sandwich" structure with L2/L5 ground layers enclosing L3 (analog signals) formed an extremely short return loop and fully shielded L4 power-layer switching noise radiation.
Thick ground, thin signal: L2/L5 ground copper was thickened to 2 oz while L3/L6 signal layers stayed at 1 oz. Overall board thermal resistance dropped 37%, and the surface temperature rise in the TEC drive area fell from 52°C to 41°C.
Material upgrade: conventional FR-4 was replaced with RO4350B (εr = 3.66, Df = 0.0037) for core layers — 15% lower high-frequency loss, and a CTE better matched to copper, reducing warpage under thermal cycling.
Final Results
The redesigned board used no expensive ceramic substrate and no stacked shielding cans, yet delivered hard results:
Under full TEC load, PT100 reading fluctuation converged to ±0.05°C (breaking through long-term drift limits in test accuracy).
Measured ENOB (effective number of bits) of the ADS124S08 jumped from 19.2 bit to 21.7 bit.
RS-485 maintained a bit error rate in the 10⁻⁹ range under 4 kV EFT strikes.
Conclusion: The Hardware Ceiling Is Set by Physical Paths
This case shows that the ceiling of temperature-control accuracy is often not set by ADC bit count, but by a few millimeters of copper routing, a 0.3 mm via diameter, and a 10 ms power-on delay.
AnyPCBA not only provides high-precision manufacturing (up to 64 layers, HDI, high-frequency hybrid stack-ups) — our DFM team also helps you identify physical landmines early in design: how to quiet the power path, where to place components, and how to build the stack-up.
If you are designing high-precision temperature control, medical sensing or high-reliability analog hardware, contact us through the AnyPCBA website and let your design go from drawing to mass production without derailing.
